Experimental study demonstrates a 200-nanometer vertical IGZO transistor architecture, indicating potential for compact drivers in micro-display technologies.
We report a bottom‐gate, top‐contact vertical‐channel In‐Ga‐Zn‐O (IGZO) thin‐film transistor (TFT) with a 200‐nm channel length defined by vertical stack thickness rather than lithographic critical‐dimension control. Conformally RF‐sputtered IGZO, together with intentionally nonconformal thermally evaporated Al contacts, enables a self‐aligned source/drain formation, whereas a SiO spacer shrinks the gate‐drain overlap capacitance by 98% without introducing ungated regions. The resulting devices achieve an on/off current ratio of , a subthreshold swing as low as 118 mV/dec, and a drive current up to 5.34 A/m at = 2 V and = 4 V, matching or surpassing state‐of‐the‐art top‐gate vertical IGZO TFTs. Two‐dimensional TCAD simulations corroborate the measured electrostatics, clarify charge‐control mechanisms in the ultrashort vertical channel, and indicate pathways—such as contact engineering and a thinner IGZO layer—to further enhance on‐current flow and saturation. These results indicate that the proposed architecture is a promising candidate for compact active‐matrix drivers in next‐generation micro‐OLED and micro‐LED displays.
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Huang et al. (2026) studied this question.
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