Influence of the Si-Layer Thickness on the Structural, Compositional and Resistive Switching Properties of SiO2/Si/SiO2 Stack Layers for Resistive Switching Memories

This work focuses on developing resistive switching (RS) devices using thermally annealed (TA) SiO2/Si multilayers (ML). Three SiO2/Si bilayers were deposited with an additional 10 nm SiO2 layer as a dielectric barrier layer on top of the ML. The SiO2 layers were 6 nm thick, while the thickness of the Si layers varied from 2, 4, and 6 nm, and were labeled as ML-62, ML-64, and ML-66, respectively. X-ray photoelectron spectroscopy analysis revealed well-defined ML structures before TA. However, after TA, samples ML-64 and ML-62 showed discontinuities due to diffusion between neighboring Si layers, increasing the dimensions of the Si-rich regions. In fact, the concentration of elemental Si (Si0) within the intermediate Si layer increases as the Si layer becomes thinner. Consequently, the size of Si-nanocrystals, created after TA, increases from 6 to 8.5 nm for ML-66 to ML-62, as confirmed by Raman and transmission electron microscopy analysis. The composition discontinuities and loss of the ML structure resulted in erratic electrical behavior, with an electroforming (EF) voltage as high as −14 V in sample ML-62. For the ML-66, which retained the ML structure, the EF voltage was reduced to −4 V, showing SET/RESET values of around ±3 V and stable electrical behavior, with an ON/OFF ratio of up to seven orders of magnitude. This demonstrates the importance of the ML design in the operation of RS devices.