Fabrication and Characterization of Back-Gate and Front-Gate Ge-on-Insulator Transistors for Low-Power Applications

Germanium (Ge) has long been regarded as a promising channel material, owing to its superior carrier mobility and highly tunable electronic band structure. The new generation of low-power electronics is approaching the formation of fully depleted (FD) transistors on Si-on-insulator (SOl) and Ge-on-insulator (GOl) substrates. In this work, we present a full process of a novel FDGOI transistor formed on a strained GOI with low defect density. This scalable and industry-compatible approach enables the formation of uniform 50 nm thick Ge layers by using spinning wet etch with ultrasmooth surfaces (RMS roughness = 0.262 nm) and a low etch-pit density of ~105 cm−2. Electrical measurements reveal excellent carrier transport properties, with back-gate (BG) transistors achieving mobilities of 550–600 cm2/V·s, while front-gate (FG) devices exhibit sharp switching behavior and steep subthreshold slopes, yielding ION/IOFF ratios up to 105. Temperature-dependent measurements further demonstrate a pronounced enhancement of device performance: the ION/IOFF ratio increases to 106, the subthreshold swing (SS) decreases from 179 mV/dec at room temperature to 137 mV/dec at 120 K, and the threshold-voltage shift with temperature is as low as 1.87 mV/K across the range of 30–300 K. Such behavior highlights the potential of band-gap engineering for precise threshold-voltage control. Taken together, these results establish GOI as a CMOS-compatible material platform and provide a solid technological basis for the development of next-generation low-power transistors beyond conventional CMOS scaling.