Electrostatic Discharge Protection Diodes with Stacked SiGe/Si Fin Field‐Effect Transistors in Gate‐All‐Around Technology

In this article, the electrostatic discharge (ESD) performance of gate‐structure‐defined diodes (gated diodes) based on stacked SiGe/Si fin field‐effect transistor (FinFET), Si channel gate‐all‐around field‐effect transistor (GAA), and SiGe channel GAA structure in GAA technology is investigated in detail by using 3D TCAD simulations. The stacked SiGe/Si FinFET demonstrates superior ESD robustness, exhibiting a significantly higher failure current (I t2 ) and the lowest on‐resistance ( R on ) among the tested structures. Meanwhile, the transmission line pulse (TLP) current conduction and failure mechanism in these gated diodes are examined through physical analysis. The results reveal that current crowding leads to early thermal failure and I t2 deterioration. Additionally, the I t2 of stacked SiGe/Si FinFET can be further improved by 6% as the Si and SiGe thickness ratios are optimized from 6/12 to 12/6 nm. These findings suggest that the optimized stacked SiGe/Si FinFET gated diode is a promising candidate for ESD protection in GAA technology.