Wafer-scale monolayer dielectric integration on atomically thin semiconductors

A promising strategy for further miniaturizing metal–oxide–semiconductor field-effect transistors is the use of ultrathin two-dimensional channel materials. However, achieving robust dielectric integration with a sub-1-nm capacitance equivalent thickness (CET) remains challenging. Here we present a wafer-scale monolayer MoO 3 , transformed from MoS 2 , which can be seamlessly integrated with atomically thin semiconductors. Its atomically flat surface and the strong electronegativity of Mo 6+ further enable the uniform deposition of high- κ dielectrics. Utilizing the 0.96-nm-CET MoO 3 /HfO 2 as the dielectric, the top-gated p-type (n-type) two-dimensional transistors show a high ON/OFF ratio of 6.5 × 10 6 (3.2 × 10 8 ) and a steep subthreshold swing of 60.8 (63.1) mV dec −1 . Statistical analysis of a 1,024-device array achieves a high yield of 92.2%. Furthermore, when monolayer MoO 3 is used as the top-gated dielectric with an ultimately scaled CET of 0.64 nm, the gate leakage current meets the low-power limit standard (1.5 × 10 −2 A cm −2 ) over the entire bias range. Our study provides a scalable approach for the integration of ultralow-CET dielectrics on two-dimensional materials, marking a critical step towards their future industrial deployment.