Key result
FPGA-based ECG signal characterization achieves sub-second latency and ~28 mW average power dissipation.
Why the study?
Automatic ECG signal characterization is computationally intensive, and low-power, online solutions are needed for patient monitoring and diagnosis.
A novel FPGA-based hardware implementation for ECG signal processing using Hermite polynomials demonstrates low latency and low power dissipation suitable for real-time applications.
Automatic ECG signal characterization is of critical importance in patient monitoring and diagnosis. This process is computationally intensive, and low-power, online (real-time) solutions to this problem are of great interest. In this paper, we present a novel, dedicated hardware implementation of the ECG signal processing chain based on Hermite functions, aiming for real-time processing. Starting from 12-bit ADC samples of the ECG signal, the hardware implements filtering, peak and QRS detection, and least-squares Hermite polynomial fit on heartbeats. This hardware module can be used to compress ECG data or to perform beat classification. The hardware implementation has been validated on a Field Programmable Gate Array (FPGA). The implementation is generated using an algorithm-to-hardware compiler tool-chain and the resulting hardware is characterized using a low-cost off-the-shelf FPGA card. The single-beat best-fit computation latency when using six Hermite basis polynomials is under 1 s with a throughput of 3 beats/s and with an average power dissipation around 28 mW, demonstrating true real-time applicability.
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Desai et al. (2021) studied this question. The FPGA implementation of ECG signal characterization achieves a latency of under 1 s, a throughput of 3 beats/s, and average power dissipation of 28 mW.
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