Non-destructive read 1T-DRAM with p–n junction gate for overcoming scaling limitations

This paper presents a p–n junction gate dynamic random-access memory (DRAM) architecture that addresses the scaling limitations of conventional 1T1C DRAM and the structural challenges of capacitor-less 1T0C and 2T0C designs. The proposed device employs a p–n junction gate, where hole accumulation modulates channel conductivity, enabling non-destructive read without a storage capacitor. This structure simplifies integration while ensuring reliable state distinction and stable operation. Simulations using Sentaurus TCAD verify the device’s performance, showing a read current margin exceeding 100 μA/μm and consistent current levels under repeated read cycles, confirming its non-destructive read capability. Retention characteristics were evaluated at 300 and 358 K, with a discernible current margin maintained under thermal stress, validating the robustness of the storage mechanism. By resolving capacitor scaling and destructive read issues, the proposed architecture provides a scalable, low-power solution for high-density memory. Its logic compatibility also highlights its potential for integration into PIM systems for future memory applications.