Scalability Prespective of Nanotube TFET Capacitorless DRAM in Sub-20 nm Regime

In this article, we have demonstrated a nanotube tunnel field-effect transistor (NT-TFET)-based one transistor (1T) dynamic random access memory (DRAM) using TCAD simulations. A low bandgap material silicon-germanium (SiGe) is used to boost the retention time (RT) and sense margin (SM) of the NT-TFET 1T DRAM in comparison to the Si storage NT-TFET 1T DRAM and past published TFET-based 1T DRAMs. Our simulation results show that the NT-TFET 1T DRAM with SiGe storage region attained RT of 100 s and 1.3 s at 27°C and 85°C, respectively for the L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SG</inf> = L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CG</inf> = 50 nm. Furthermore, the NT-TFET 1T DRAM still acquires RT of 200 ms when the storage region or core gate length is reduced to 10 nm.