Revisiting Lateral-BTBT Gate-Induced Drain Leakage in Nanowire FETs for 1T-DRAM

In this work, we revisit the lateral band-to-band tunneling (L-BTBT) gate-induced drain leakage (GIDL) in gate-all-around (GAA) nanowire field-effect transistors (NWFETs) which is otherwise detrimental to logic operation and propose design guidelines for amplifying hole accumulation and floating body effects for realizing scalable one-transistor (1T)-dynamic random access memory (DRAM) with appreciable sense margin, high retention, and low write energy. The performance of the proposed NWFET-based 1T-DRAM was evaluated using calibrated 3-D TCAD simulations. The proposed NWFET-based 1T-DRAM exploiting L-BTBT GIDL for write operation exhibits an ultralow write energy of 3.78 fJ, a high sense margin of 89.19 nA, and an appreciable retention time of 5 ms even for an ultrashort gate length of 20 nm.