SensTDDP: A Timing Sensitivity Analysis Framework with Application to Timing-Driven Detailed Placement

Timing convergence is paramount for the feasibility of VLSI circuit design, which is highly dependent on timing optimization during VLSI placement. Timing-driven placement usually achieves timing optimization by optimizing the locations of timing-violating cells. These cells are often characterized by timing criticality in global and detailed placement. However, we find that this metric cannot accurately capture the cells whose movement will affect the overall timing results. To bridge this gap, this paper proposes a timing sensitivity analysis framework to precisely quantify the impact of physical objects (pins, combinational cells, FFs, and nets) on overall timing. Within this framework, we derive the TNS and WNS sensitivities of pins, combinational cells, FFs and nets. Moreover, we introduce a total timing sensitivity metric to estimate how much physical objects affect the total timing. To validate its effectiveness, the timing sensitivity analysis framework is utilized to refine the combinational cell movement techniques in Rsyn [6, 7]. Moreover, we develop an FF classification and moving scheme based on the timing sensitivity analysis framework, to further enhance timing optimization. Experimental results show that our approach achieves remarkable average improvements in TNS and WNS without compromising total wirelength and routability, compared to the state-of-the-art timing-driven detailed placer.