A 40‐nm CMOS Inductorless LNA for 5–6 GHz WLAN Applications With Controlled Positive‐Feedback and Three‐Stage Noise Cancellation

To meet the stringent requirements of modern wireless standards like Wi‐Fi 6/7, this paper presents an inductorless low‐noise amplifier (LNA) for 5–6 GHz WLAN applications in 40‐nm CMOS. Addressing the inherent trade‐offs in inductorless topologies, the proposed design is distinguished by a physics‐circuit co‐design strategy. Specifically, the architecture synergistically integrates a self‐regulating positive‐feedback loop with a three‐stage noise‐canceling technique to boost gain while aggressively suppressing thermal noise. Concurrently, it exploits a mobility‐compensated derivative superposition mechanism to create an intrinsic “linearity sweet spot,” enhancing dynamic range without area‐consuming components. Measurement results demonstrate a peak voltage gain of 20.9 dB, a minimum noise figure of 2.09 dB, and an IIP3 of +4.21 dBm, all while consuming only 6.6 mW within a compact core area of 0.0389 mm 2 . Ultimately, the design attains a state‐of‐the‐art figure‐of‐merit and serves as a valuable reference for future area‐constrained wideband RFIC designs seeking to break performance boundaries.