Sorting plays a crucial role in various applications, including high-performance computing, image processing, and network systems. Traditional sorting algorithms are efficient in software but can be a computational bottleneck in hardware implementations. This paper laid out various sorting architectures like Odd-Even Sort, Bitonic Sort, and Odd- Even Merge Sort with a detailed overview of their area, power and performance metrics. A Scalable and Hardware- Efficient Bidirectional Hybrid Sorting of Odd-Even Merge Sort and Bidirectional Insertion Sort. These designs were created using Verilog HDL simulated in Cadence Incisive and synthesized in Genus. Proposed architecture reduces area, power, and delay by up to 1.63%, 3.68%, and 16.93%, respectively, over existing design. The comparison made in the analysis of these data indicates the effectiveness of the proposed methodology in terms of resource allocation as well as preservation of the high efficiency of the sorting operation, indicating its applicability in such systems where resource allocation is inadequate in the comparison mode applied.
Chrysolite et al. (Wed,) studied this question.