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January 29, 2026Journal of Electronic Testing

A Robust AES Implementation using FPGA with Enhanced Security Features

Arulmurugan Azhaganantham Vivek Balasubramaniam

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Key Points

The AES implementation enhances security features, improving data protection against threats.
Key metrics include a notable increase in encryption speed by 30% while maintaining data integrity.
The method employs FPGA for hardware implementation, optimizing encryption algorithms for better performance.
This highlights the potential for broader application of enhanced security features in various electronic systems.

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Implication

Observational analysis of AES implementation enhances security in FPGA technology, suggesting improved data protection.

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Cite This Study

Azhaganantham et al. (2026) studied this question.

synapsesocial.com/papers/69a75da7c6e9836116a27d5a https://doi.org/10.1007/s10836-026-06216-7

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