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February 3, 2026Integration

Algorithm-hardware co-design of binary neural network for efficient super resolution on FPGA

Yuanxin Su Yihong Wang Yushan Pan Nan Xiang Zhijie Xu Jeremy Smith Xinfei Guo

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Key Points

The efficient super resolution achieved on FPGA demonstrates significant improvements in processing speed.
Notably, the algorithm, combined with hardware co-design, allows for enhanced performance in neural network tasks.
Analysis involved a systematic approach using binary neural networks to optimize FPGA resources for better applications.
This co-design approach highlights the potential benefits of merging algorithm development with hardware specifications for performance.

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Implication

Observational analysis showcases efficient super resolution via binary neural network on FPGA, implying faster processing capabilities.

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Cite This Study

Su et al. (2026) studied this question.

synapsesocial.com/papers/69a75ff4c6e9836116a2c544 https://doi.org/10.1016/j.vlsi.2026.102674

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