This research demonstrates improved electrical performance in Si/HfO2 MOS devices using high-pH fluoride-treated SiO2 surfaces, suggesting a novel interface engineering approach.
Interface engineering at the silicon/high-κ dielectric interface is a critical issue for achieving a superior electrical performance in Si-based MOS devices. The conventional HF-last process produces a hydrogen-terminated Si surface, which leads to complex interfacial reactions during ALD deposition and postannealing, resulting in the formation of silicide, silicate, and oxygen vacancies that degrade electrical performance. Here, we demonstrate an ultrasmooth, subnanometer (∼2 monolayers) chemical SiO₂ layer formed by a simple high-pH fluoride solution treatment following standard RCA cleaning. The tailored fluoride chemistry (NH₄F/(NH₄)₂SO₃/NH₄OH) provides an ultralow, nonlinear, and self-limiting etching characteristics that effectively eliminate hillock-like surface features, yielding an atomically smooth SiO₂ surface (Rq = 0.06 nm). HfO₂ gate stacks fabricated on this surface exhibit markedly improved interfacial properties compared to the HF-last substrate without substantial compromise in equivalent oxide thickness (EOT), indicating a significant (∼80%) reduction in interface trap density, suppressed fixed oxide charges (∼60% reduction) and hysteresis, enhanced breakdown voltages, and a transition from trap-controlled space-charge-limited conduction to tunneling-dominant carrier transport. Cross-sectional high-resolution scanning transmission electron microscopy (HRSTEM) and energy-dispersive X-ray spectroscopy (EDS) confirmed an atomically smooth and abrupt SiO₂/HfO₂ interface without element intermixing, even after postmetallization annealing. This work establishes a simple, industry-compatible strategy for achieving an atomically smooth SiO₂ interlayer, overcoming the challenges of heterogeneous growth and roughness in chemical SiO₂, thereby enabling robust interface control in Si/high-κ gate stacks and providing a scalable pathway for advanced Si CMOS technology.
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Chang et al. (2026) studied this question.
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