A 16‐Bit 80‐MS/s Tri‐Stage Pipelined‐SAR ADC With Non‐Binary Redundancy CDAC and Wide Common Mode Input Ring Amplifier

This paper presents a 16‐bit 80 MS/s tri‐stage pipelined‐successive approximation register (pipelined‐SAR) ADC with non‐binary redundancy CDAC and wide common mode input ring amplifier. To enhance robustness against common mode input variations, a wide common mode input ring amplifier is proposed as the residue amplifier. The first‐stage sub‐ADC employs a non‐binary weighted capacitor array, which can tolerate the settling error of the DAC, thereby reducing the settling time and improving the speed. The ADC is designed in the 65 nm CMOS process and occupies an active area of 0.168 mm 2 . At 80 MS/s and Nyquist‐rate input, the prototype ADC achieves SNDR and SFDR of 75.3 and 83.3 dB respectively, with 5.3 mW power consumption only. The prototype ADC achieves Walden and Schreier figure of merit of 13.8 fJ/conversion‐step and 174 dB, respectively.