What question did this study set out to answer?

The research aims to explore and analyze low-power techniques for energy-efficient edge processing using flash-based SoC FPGAs.

March 13, 2026Open Access

Exploiting Low-Power Techniques of a Flash-Based SoC FPGA for Energy-Efficient Edge Processing

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Authors

MKMuhammad Iqbal KhanVrije Universiteit Brussel NMNicolas Roberto Becerra MachadoVrije Universiteit Brussel ANAbdessamad NassihiVrije Universiteit Brussel

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Implication

This work explores low-power techniques to reduce energy consumption in energy-efficient edge systems, highlighting their implications for performance.

Key Points

The research aims to explore and analyze low-power techniques for energy-efficient edge processing using flash-based SoC FPGAs.
Measured low-power modes across three architectural approaches: SW, co-design, and HW.
Implemented frequency scaling on a Microchip Smartfusion2 platform.
Tested with a low-duty-cycle heart-rate monitoring workload.
Total energy for low-duty-cycle workloads is dominated by the idle phase.
Combining fabric Flash*Freeze with processor sleep minimizes energy consumption.
Main-clock downscaling reduces active-phase current but has limited effects on idle consumption when low-power modes are applied.

Cite This Study

Khan et al. (2026) studied this question.

synapsesocial.com/papers/69b3ac6002a1e69014ccdfd9 https://doi.org/10.3390/app16062648

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Implication

This work explores low-power techniques to reduce energy consumption in energy-efficient edge systems, highlighting their implications for performance.

Exploiting Low-Power Techniques of a Flash-Based SoC FPGA for Energy-Efficient Edge Processing

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Member takes

Implication

Key Points

Cite This Study

Exploiting Low-Power Techniques of a Flash-Based SoC FPGA for Energy-Efficient Edge Processing

Discussion

Member takes

Implication

Key Points

Cite This Study

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