Design and Stability Optimization of 6T SRAM Using Dual Gate Junctionless FETs

In this work, a static random-access memory (SRAM) is investigated by using the dual-gate junctionless field-effect transistors (DGJLFETs). The device uses a double-side gate structure to offers superior gate controllability compared to traditional TFETs, that reduces the leakage in off-state. To avoid complexity in the fabrication process, the junctionless FET is designed with uniform doping. This junctionless architecture offers low DIBL and subthreshold swing (SS), and avoid the voltage roll-off for short-channel devices. To design the SRAM, both N-DGJLFET and P-DGJLFET are designed and their analog characteristics are analyzed. The n-type device exhibits ION/IOFF ratio of ~1012 and SS as ~10 mV/decade. A 6T-SRAM is designed and operated at VDD = 0.8 V, achieving 23% higher stability than previously proposed UTB-Si JLFET. The DGJLFET based SRAM exhibits reasonable stability even when operated at VDD = 0.6 V.