Adiabatic SRAM with a large margin of VT variation by controlling the cell-power-line and word-line voltage

An adiabatic 1-kb SRAM circuit was designed, which enables gradual charging during writing and reading while maintaining a large VDD so that the problems of VT variation and electromigration in the nanocircuit can be resolved. In the writing mode, the voltage of the memory cell power line is reduced to ground gradually using a high-resistivity nMOSFET, and we turn off the nMOSFET so that the memory cell power line is set in a high-impedance state. Then, we can write data easily by inputting adiabatic signal from one bit line, while the other bit line is set to ground. For reading, a verifying operation is proposed for resolving the electromigration problem. The word line voltage is changed stepwise while the voltages of the bit lines are verified. The reading method enables a gradual current flow in the memory cell. We designed the cell layout and found that there is no area penalty. In addition, a new charge recycle circuit with tank capacitors is proposed.