The rapid growth of 5G necessitates wireless receivers capable of high-speed, low-latency communication under complex channel conditions. Traditional receivers struggle with the performance–complexity trade-off in massive MIMO systems, where linear detectors underperform and maximum likelihood (ML) detection becomes computationally prohibitive. Deep-learning-based model-driven approaches have demonstrated a favorable balance between detection performance and computational cost. However, despite their algorithmic promise, the transition of these learned detectors into practical, real-time systems is critically hampered by inefficient hardware mapping, resulting in suboptimal throughput, high resource overhead, and limited scalability. To bridge this gap, this paper presents LwAMP-Net, a dedicated FPGA accelerator for a lightweight learned AMP detector. We propose a modular and multi-mode hardware architecture for LwAMP-Net, featuring an outer-product-based dataflow that mitigates pipeline stalls and multi-mode processing elements that adapt to diverse computation patterns. These innovations jointly enhance computational parallelism and resource utilization on the FPGA. Implemented on a Xilinx XC7VX690T FPGA for a 128 × 8 MIMO system with 16QAM, the accelerator achieves a 49.2% higher normalized throughput per iteration, an 85.4% improvement in throughput per LUT slice, and a 12.7% improvement in throughput per DSP compared to the state-of-the-art methods. This work provides a complete architectural solution for deploying high-performance, hardware-efficient learned MIMO detectors in real-world systems.
Lin et al. (Thu,) studied this question.