Answers are grounded in this paper and cite their sources.
Gate-first integration of tunable work function metal gates of different thicknesses (3-20 nm) into high-k/metal gates CMOS FinFETs was demonstrated to achieve multiple threshold voltages (V Th ) for 32-nm technology and beyond logic, memory, input/output, and system-on-a-chip applications. The fabricated devices showed excellent short-channel effect immunity (drain-induced barrier lowering ~40 mV/V), nearly symmetric V Th , low T inv (~1.4 nm), and high I on (~780 ¿A/¿m) for N/PMOS without any intentional strain enhancement.
No takes yet. Share an insight, caveat, or question.
Hussain et al. (2010) studied this question.
Synapse has enriched 10 related papers. Consider them for comparative context: