A circuit design reveals low power consumption and stable operation in high resistance environments, indicating efficiency for current-mode applications.
A 0.3 V nanowatt CCII− is presented in 0.18 μm TSMC CMOS, targeting ultra-low-power current-mode interfaces. Post-layout extracted simulations demonstrate correct conveying operation with a total DC power consumption of less than 2.40 nW. The low-frequency tracking factors evaluated at 1 Hz are β0=0.9452 (−0.48 dB) and α0=0.9609 (≈−0.35 dB), with −3 dB bandwidths of 22.95 kHz and 63.95 kHz for the voltage and current transfers, respectively. Small-signal extraction confirms the intended impedance profile, yielding RX=46.73 MΩ, RZ=1.204 GΩ, and a very high input resistance RY=392 GΩ. Robustness is verified through full PVT and mismatch analyses, showing stable functionality across process corners, a 0–80 °C temperature range, and 270–330 mV supply variations while maintaining nanowatt-level dissipation.
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Nicolini et al. (2026) studied this question.
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