High-Performance Dual Gate Amorphous InGaZnO Thin Film Transistor With Top Gate to Drain Offset

We report the dual gate (DG) amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor (TFT) with a top-gate (TG) drain offset ( <tex-math notation="LaTeX">LTG(Off) </tex-math> ) structure under dual-gate driving. The TFT shows an on/off current ratio of <tex-math notation="LaTeX">~ 10^7 </tex-math> , subthreshold swing of 0.23 V/dec, and field-effect mobility ( <tex-math notation="LaTeX">μ FE </tex-math> ) of 14.6 cm 2 /Vs when <tex-math notation="LaTeX">L_ TG(Off) </tex-math> is 5 <tex-math notation="LaTeX">μ m </tex-math> , which is 30% reduction compared to the conventional DG TFT with no drain offset ( <tex-math notation="LaTeX">μ FE=20.9 </tex-math> cm 2 /Vs). The Technology computer-aided design simulation indicates the electron concentration of <tex-math notation="LaTeX">~ 10^16 </tex-math> /cm 3 at the offset region near top gate insulator/a-IGZO interface when <tex-math notation="LaTeX">L_ TG(Off) </tex-math> is 5 <tex-math notation="LaTeX">μ m </tex-math> . The fabricated TFT exhibits stable performance under positive bias temperature stress with a threshold voltage shift of +0.1 V.