ABSTRACT This letter presents a four‐channel low‐noise neural signal amplifier for the hippocampus prosthetic chip. A new time‐division multiplexing structure is proposed, and the functions and performance of the chip are verified through layout and testing. The test results show that the LNA achieves an input referred noise of 4.43 µV rms within the bandwidth range of 60 Hz to 10.9 kHz, 5.5 µW power consumption and 0.023 mm 2 area per channel, an electrode direct offset tolerance of 40 mV and an input impedance of 52 MΩ at 10 kHz frequency. Furthermore, the LNA attains a total harmonic distortion (THD) value of 0.94%, and a noise efficiency factor value of 3.8. ASIC is implemented using SMIC 40 nm LLRF CMOS technology.
An et al. (2026) studied this question.