Key points are not available for this paper at this time.
NAND flash has become the choice of storage media as the world enters the era of digital transformation and artificial intelligence. The request to keep NAND on a sustainable scaling path has never been stronger. In this paper, the status and the trend for NAND scaling, which includes both the array scaling as well as the CMOS scaling, are reviewed. The knobs that govern both array and CMOS scaling are introduced. The tradeoffs among the knobs are considered. System performance and its requirements to NAND scaling is also discussed. Finally, the paper ends with a conclusion that there is a path for both cost and performance scaling well into the next decade with current gate all around (GAA) architecture.
Heineck et al. (Sun,) studied this question.