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This research aims to demonstrate the capabilities of an integrated passive silicon photonics reservoir for various computations.

March 24, 2014Nature CommunicationsOpen Access

Experimental demonstration of reservoir computing on a silicon photonics chip

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This research aims to demonstrate the capabilities of an integrated passive silicon photonics reservoir for various computations.
Proposed an integrated passive silicon photonics chip for reservoir computing.
Conducted experiments and simulations to evaluate performance.
Performed 5-bit header recognition and isolated spoken digit recognition.
Achieved header recognition at speeds up to 12.5 Gbit/s without power consumption in the reservoir.
Demonstrated the ability to perform arbitrary Boolean logic operations with memory.
Indicated scalability to larger networks and speeds exceeding 100 Gbit/s.

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Experimental demonstration of an integrated passive silicon photonics reservoir performing high-speed computations.

Vandoorne et al. (2014) studied this question.

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