Design Compact 6-Bit Phase Shifter for 6G Upper-Mid Band Using 130-nm SOI

This paper presents the design and measurement of a 6-bit phase shifter for 6G upper-mid band communication implemented using a 130 nm SOI process. The proposed phase shifter operates in the 6.8~8.8 GHz frequency range and achieves a compact chip area by utilizing stacked inductors. The measurement results demonstrate a low insertion loss of 4.7 dB at 7.8 GHz and a low root mean square (RMS) phase error of 3.7°, with an RMS amplitude variation of 0.3 dB. The total chip size, including pads, is 1.1×0.56 mm.