Low-Power Direct Hardware Implementation of Logic Controllers Using Standard Languages

The paper shows the methodologies of implementing a high-performance low-power logic control system designed with the use of standard languages like LD and SFC (according to the IEC61131-3 standard) directly in hardware utilizing FPGA devices. The essential idea is to convert the sequential sentences of a language to parallel computations and then map them to a dedicated hardware structure. The flexible graph-based method of language mapping is shown. It enables extracting control and data flow from language sentences. The direct hardware mapping technique enables building not only a high-performance structures but also a low-power implementations. All implementations retain a very short response time consisting of several clock cycles (from 3 to 7). The proposed low-power mapping strategies enable power saving up to 10 times while retaining processing performance. The obtained results are compared with a standard implementation using a benchmark program set. The paper is concluded with a comparison of the performance and energy consumption for the proposed implementation strategies.