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April 30, 2026JSTS Journal of Semiconductor Technology and Science0 citations

ML-Driven Optimization of Standard Cells for Performance and Timing in Advanced Nodes

ML-Driven Optimization of Standard Cell Performance and Timing in Advanced Nodes

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Randomized trial demonstrates performance improvement in standard cells, highlighting machine learning implications.

This research aims to optimize standard cell performance and timing in advanced nodes using machine learning techniques.
Developed a machine learning-based methodology for standard cell optimization.
Performed post-layout simulations with parasitic component extraction (PEX) for delay and power calculations.
Trained an artificial neural network (ANN) and used multi-objective Bayesian optimization to refine standard cell designs.
For HP INV cells, delay reduced by up to 23.2%; for LP NAND2 cells, power reduced by 10.3%.
Rise-fall delay balance improved by over 15% in NAND2/NOR2 cells.
Significant improvements in delay and power efficiency were observed in optimized test circuits including a 7-stage ring oscillator and a 4-bit ripple carry adder.

Jeong et al. (2026) studied this question.

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April 30, 2026JSTS Journal of Semiconductor Technology and Science0 citations

ML-Driven Optimization of Standard Cell Performance and Timing in Advanced Nodes

View Full Paper

Ask AI

Bookmark

Authors

Randomized trial demonstrates performance improvement in standard cells, highlighting machine learning implications.

This research aims to optimize standard cell performance and timing in advanced nodes using machine learning techniques.
Developed a machine learning-based methodology for standard cell optimization.
Performed post-layout simulations with parasitic component extraction (PEX) for delay and power calculations.
Trained an artificial neural network (ANN) and used multi-objective Bayesian optimization to refine standard cell designs.
For HP INV cells, delay reduced by up to 23.2%; for LP NAND2 cells, power reduced by 10.3%.
Rise-fall delay balance improved by over 15% in NAND2/NOR2 cells.
Significant improvements in delay and power efficiency were observed in optimized test circuits including a 7-stage ring oscillator and a 4-bit ripple carry adder.

Jeong et al. (2026) studied this question.

View Full Paper

Ask AI

Bookmark