NH 3 -annealed atomic-layer-deposited silicon nitride as a high-k gate dielectric with high reliability

Extremely thin (equivalent oxide thickness, Teq=1.2 nm) silicon-nitride high-k (εr=7.2) gate dielectrics have been formed at low temperatures (⩽550 °C) by an atomic-layer-deposition (ALD) technique with subsequent NH3 annealing at 550 °C. A remarkable reduction in leakage current, especially in the low dielectric voltage region, which will be the operating voltage for future technologies, has made it a highly potential gate dielectric for future ultralarge-scale integrated devices. Suppressed soft breakdown events are observed in ramped voltage stressing. This suppression is thought to be due to a strengthened structure of Si–N bonds and the smoothness and uniformity at the poly-Si/ALD-silicon-nitride interface.