Channel-Side Interlayer Engineering in Laminated Fe-FETs: Trap-Driven Optimization of Memory Window, Retention, and Disturb in Ferroelectric NAND Flash

In this work, we demonstrate for the first time that laminated Fe-FETs for Fe-NAND exhibit a distinct behavior: despite the common expectation that higher-<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</tex> channel-side interlayers (C-ILs) enhance reliability by lowering the equivalent oxide thickness (EOT), lower-<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</tex> C-ILs instead deliver superior memory-window (MW), retention, and pass-disturb performance. We systematically compare three different pure-oxide C-ILs <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(SiO₂, Al₂ O₃, HfO₂)</tex> through experiments and TCAD modeling to elucidate trap-driven reliability. The results reveal that although high- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</tex> C-IL layer reduce EOT, their higher trap densities cause MW narrowing, faster retention loss, and enhanced charge trapping. Devices with an <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8 ~nm Hf0.5 Zr0.5 O₂ / 3 ~nm Al₂ O₃ / 8 ~nm Hf0.5 Zr0.5 O₂</tex> stack and 1.5 nm C-ILs confirm that the low <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</tex> oxide achieves the most stable operation, exhibiting 15% larger MW, 1% retention loss at 1 ks, and 44% lower electron-trapping-induced disturb degradation after 106 passdisturb cycles. This behavior arises from trap-induced charges that outweighs the expected benefit of high dielectric constant, as confirmed by TCAD simulations. These findings highlight C-IL trap engineering as a key enabler for reliable, high-density FeNAND integration and clarify how channel IL-dependent traps govern reliability in laminated Fe-FETs.