Synapse
⌘+K
Synapse
PulseExploreClubsResearchersJournals
Instagram
HomeClubsExplore
February 1, 2007

A 72mW 0.03mm2 Inductorless 40Gb/s CDR in 65nm SOI CMOS

View Full Paper
Ask AI
Bookmark
Share

Authors

TTThomas ToiflUniversity of British ColumbiaCMChristian MenolfiIBM Research - ZurichPBPeter BuchmannIBM (United States)

Discussion

Loading...

Member takes

Implication

Key Points

Key points are not available for this paper at this time.

Cite This Study

Toifl et al. (2007) studied this question.

synapsesocial.com/papers/6a0fe660d8c5cf602efd5180https://doi.org/10.1109/isscc.2007.373376
View Full Paper
Ask AI
Bookmark
Share

Also Consider

Synapse has enriched 4 closely related papers on similar clinical questions. Consider them for comparative context:

  1. 1A semidigital dual delay-locked loop1997 · 337 citations
  2. 2A 40-Gb/s clock and data recovery circuit in 0.18-μm CMOS technology2003 · 136 citations
  3. 3A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS B.2006 · 45 citations
  4. 4A 0.18-μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems2003 · 56 citations