A Reproducible FPGA-to-Silicon Verification Methodology for an Embedded SoC Platform in 28 nm CMOS

Many System-on-Chip (SoC) studies rely solely on simulation and tool-based results, encountering unexpected failures during post-silicon validation. In particular, silicon-level demonstrations of Hardware/Software (HW/SW) functional equivalence, which confirms that an FPGA-validated design operates identically on an ASIC with the same firmware, remain extremely rare. This work proposes a reproducible FPGA-to-silicon verification methodology that establishes HW/SW functional equivalence at the silicon level by applying an identical firmware source code, device driver, and memory map to both platforms. The methodology is validated on an Arm Cortex-M0-based SoC platform fabricated in Samsung 28nm Low Power Plus (LPP) CMOS technology with a dual Inter-Integrated Circuit (I2C) interface. The fabricated chip integrates two 64KB on-chip memories within a core area of 653 μm × 769 μm, operates at 125 MHz, and consumes 17.5 mW at the optimal operating point of 1.0 V. The primary contributions are: (1) a reproducible FPGA-to-silicon HW/SW functional equivalence verification methodology based on shared firmware source code, device driver, and memory map across both platforms, (2) silicon-measurement-based performance characterization with verified experimental data, (3) a reproducible design methodology documenting the complete flow from FPGA verification through ASIC fabrication, including static timing closure, place-and-route, and physical verification, and (4) an extensible SoC platform architecture enabling researchers to integrate and validate their own Intellectual Property (IP) via Advanced High-performance Bus (AHB) and I2C interfaces.