A Low-Offset Sense Amplifier with Self-Adaptive Calibration and Dynamic Body-Biased Mitigation Technology for Enhanced SRAM Read Performance

Offset voltage (VOS) is a critical parameter of sense amplifiers (SAs), determining both the read reliability and performance of SRAM. This paper proposes SC-DISBSA, a low-VOS SA that combines self-adaptive calibration with dynamic body bias technology. Based on the linear relationship between the transfer gate voltage and VOS, a three-step self-adaptive calibration algorithm is established. Supported by the calibration control circuit, this approach quantitatively calibrates circuit mismatch while dynamic body bias further suppresses remaining variations. Under a 28 nm CMOS process, the VOS standard deviation (σOS) of SC-DISBSA remains below 3.1 mV across a 0.7 V to 1.1 V supply range, representing reductions of 49.9% and 69.3% compared to the voltage-latch SA (VLSA) and current-latch SA (CLSA), respectively. At a typical case (TT/0.9 V/27 °C) with a BL differential (ΔVBL) of 6σOS, SC-DISBSA reduces the required bitline discharge delay by 51.7% and improves average read sensing power by 24.9% compared to VLSA. By adopting an non-conventional bitline power supply strategy, SC-DISBSA decreases worst case (FF/1.1 V/125 °C) static power by 36.8% relative to VLSA. Additionally, it reduces gate area by 18.9%. Overall, SC-DISBSA effectively optimizes SRAM read latency and power efficiency.