What question did this study set out to answer?

Describe the architecture, implementation, and operating metrics of a high-speed custom 64-bit CMOS microprocessor capable of dual-instruction execution.

January 1, 1992IEEE Journal of Solid-State Circuits

A 200-MHz 64-b dual-issue CMOS microprocessor

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Authors

DDD. DobberpuhlMonterey Technologies (United States)RWRichard T. WitekDigital Wave (United States)RAR. AllmonEP Energy (Czechia)

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Implication

Engineering design report demonstrates a 200-MHz dual-issue 64-bit CMOS microprocessor, indicating viable high-performance computing through pipelined execution and dual instruction processing.

Key Points

Describe the architecture, implementation, and operating metrics of a high-speed custom 64-bit CMOS microprocessor capable of dual-instruction execution.
Fabricated the microprocessor using a 0.75-µm CMOS process with three levels of metallization optimized for 3.3-V operation.
Integrated separate 8-KB instruction and data caches with a fully pipelined floating-point unit supporting IEEE and VAX formats.
Engineered execution hardware to issue two instructions per cycle across scoreboarded integer, floating-point, address, and branch units.
Achieved peak throughput of 400 MIPS and 200 MFLOPS at an operating frequency of 200 MHz.
Integrated 1.68 million transistors on a 16.8 mm × 13.9 mm die with total power dissipation of 30 W at 200 MHz.

Cite This Study

Dobberpuhl et al. (1992) studied this question.

synapsesocial.com/papers/6a10d25a2c0ee39daeee4158 https://doi.org/10.1109/4.165336

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Implication

Engineering design report demonstrates a 200-MHz dual-issue 64-bit CMOS microprocessor, indicating viable high-performance computing through pipelined execution and dual instruction processing.

A 200-MHz 64-b dual-issue CMOS microprocessor

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Implication

Key Points

Cite This Study

A 200-MHz 64-b dual-issue CMOS microprocessor

Discussion

Member takes

Implication

Key Points

Cite This Study

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