A Low Noise 8.3-Mpixel CMOS Image Sensor With Selectable Multiple Sampling Technique by 5.36 GHz Global Counter and Dual Latch Skew Canceler

This document presents a CMOS image sensor (CIS) with a high-speed single slope ADC(SS-ADC) that has a novel high-speed counter and can reduce temporal noise in a wide range of frequency components by enabling correlated multiple sampling (CMS) and digital correlated double sampling (DCDS) at high frame rates. The test chip was fabricated in 55nm process and has 8.3M pixels. The counter was confirmed to operate at a frequency equivalent to 5.36GHz. It uses a circuit and dedicated counter code that suppresses differential non-linearity (DNL) deterioration due to faster counter speeds. When CMS is performed 4 times at 30 frames per second (fps), the random noise is 187uVrms, which is a 31% improvement in noise compared to when CMS is not performed.