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In this paper, a single-phase solid-state transformer (SST) system based on a multilevel topology using multi-cell is proposed. The proposed SST has an automatic capacitor voltage balancing capability on a primary side due to use of a resonant DC-DC converter. The main contribution of this paper is revealing the fundamental loss design of the proposed topology connected with a 6.6-kV grid. It is predicted that the maximum efficiency of full model SST reaches 99%. The miniature model SST is tested to confirm the fundamental operation with an input voltage of 1320 V, which is 1/5 of the full model. As a result, the sinusoidal input current is obtained with a total harmonic distortion of 4.3%. Besides, the bidirectional operation is verified. Then, it is confirmed that the primary side capacitor voltage of each cell is kept constant and balanced without a voltage balance control. Moreover, the loss analysis is derived in each part and compared with that of the experimental result. The error of the loss between the experimental result and the calculation is less than 5%.
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Itoh et al. (2018) studied this question.
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