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This research aims to reduce excessive off-state leakage in carbon nanotube FETs using a novel asymmetric gate design.

May 26, 2026NanomaterialsOpen Access

Suppressing Gate-Induced Drain Leakage with an Asymmetric Gate Design in HiPco CNT FETs

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This research aims to reduce excessive off-state leakage in carbon nanotube FETs using a novel asymmetric gate design.
Introduced a small-diameter HiPco CNT channel with an asymmetric gate architecture.
Conducted calibrated TCAD simulations for NMOS and PMOS operation.
Evaluated performance metrics such as off-current, on-current, and on-off ratio at different technology nodes.
Achieved an ultralow off-current of 10 fA/µm and an on-current of 1.08 mA/µm at the 90 nm node.
At the scaled 28 nm node, the PMOS had 3 mA/µm on-current and 6 pA/µm off-current with an on-off ratio of 5 × 108.
Demonstrated significant scalability potential for future nano-electronic applications.

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Randomized trial demonstrates improved performance in carbon nanotube transistors, suggesting scalability for future electronics.

Ma et al. (2026) studied this question.

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