Parameter Extraction of Extended Floating Gate Field-Effect Transistors (EGFETs): Estimating the Threshold Voltage, Series Resistance, and Mobility Degradation From I–V Measurements

Extended floating gate field-effect transistors (EGFETs) are CMOS-compatible floating gate devices capable of detecting charges on their sensing area by the relative shifts in current–voltage ( <tex-math notation="LaTeX">I </tex-math> – <tex-math notation="LaTeX">V </tex-math> ) characteristics. The <tex-math notation="LaTeX">I </tex-math> – <tex-math notation="LaTeX">V </tex-math> shifts are generally computed by measuring the EGFET parameters in the strong inversion region of operation. This could lead to errors in estimating the device sensitivity because it ignores the mobility degradation and series resistance effects. Our goal is to model these parasitic effects and extract the key device parameters. We derive an analytical <tex-math notation="LaTeX">I </tex-math> – <tex-math notation="LaTeX">V </tex-math> model for EGFETs in the linear region of transistor operation, accounting for both the mobility degradation and series resistance effects. Three methods are presented to estimate the key parameters, namely, the threshold voltage, series resistance, surface roughness parameter, low-field mobility, and effective mobility from the <tex-math notation="LaTeX">I </tex-math> – <tex-math notation="LaTeX">V </tex-math> characteristics, gate transconductance, and drain conductance. The peak transconductance method is used as a benchmark for comparing the extracted threshold voltages. Silicon-based EGFET devices are fabricated, and their <tex-math notation="LaTeX">I </tex-math> – <tex-math notation="LaTeX">V </tex-math> characteristics are measured with deionized (DI) water and three polyelectrolytes. From the <tex-math notation="LaTeX">I </tex-math> – <tex-math notation="LaTeX">V </tex-math> data, the parameter extraction methods are used to compute the values of the key parameters, and the suitability of each method is discussed. The gate transconductance methods show good agreement between the values for the key parameters, while the drain transconductance method gives lower values of the key parameters. There is scope to improve the presented methods by incorporating the effects of substrate bias and asymmetric series resistance for new extended-gate device architectures, including solution-based organic field-effect transistors.