Design and Implementation of an AES Hardware Encryption Core

The Advanced Encryption Standard (AES-128) is widely used in high-speed secure communication systems, requiring efficient ASIC-oriented hardware implementations. To ensure that the implementation achieves full functional correctness and coverage, this work provides an AES-128 hardware implementation in Systemverilog, which has been tested using an environment based on the Universal Verification Methodology (UVM). Post-synthesis evaluation provides realistic timing, area, and power metrics using Cadence Genus. Pipelining techniques were employed to reduce the critical path delay, along with enabling maximum operating frequency. Competitive area utilisation and power efficiency were also maintained. The proposed architecture demonstrates improved timing efficiency compared with representative FPGA-based implementations. This paper presents a fully pipelined ASIC-oriented AES-128, 300 ps combinational critical path delay and 1.39 GHz operating frequency.