This paper presents the design and FPGA implementation of an ultra-low-power maritime obstacle detection accelerator targeting the PYNQ-Z2 platform (Xilinx Zynq XC7Z020-CLG400-1). The system processes 64×64 greyscale maritime images through a five-stage synchronous streaming pipeline in Verilog HDL, consuming zero DSP slices by performing all computation using only addition, subtraction, and comparison. A systematic comparative study across 20 configurations — five classical gradient operators combined with four preprocessing methods — on 2,000 maritime images and 40,000 classification trials identified the Prewitt operator with bilateral filtering as the optimal configuration, achieving 88.6% accuracy, 88.6% F1 score, AUC of 0.9387, and class separation ratio of 3.00. A statistically calibrated classification threshold of 127,824 is embedded in hardware. The design achieves 0.126 W total on-chip power at 100 MHz — a 17-fold reduction compared to a CNN-based accelerator on the same device — with post-implementation Worst Negative Slack of +0.317 ns, zero timing violations, and a frame latency of 40.98 microseconds (approximately 24,400 frames per second). A counter-intuitive finding demonstrates that CLAHE preprocessing systematically degrades F1 score by a mean of 9.7 percentage points across all five operators tested.
L et al. (Thu,) studied this question.