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Security is critical to today's interconnected world, and hardware protection is equally important as security at the network and system levels. Silicon physically unclonable functions (PUFs) are increasingly used as a hardware root of trust and an entropy source for cryptography applications. In those applications, the reliability of PUF output is key to a successful implementation. Both weak and strong PUFs obtain output by amplifying analog signals from physical properties on IC blocks (e.g. propagation delay, ring oscillator, time-controlled oxide breakdown 1 or threshold voltage of SRAM transistors 2,3,4). These physical measurements are by nature sensitive to environmental conditions, such as temperature, operating voltage, thermal/interface noise of transistors, process corners and aging. As a result, it is difficult to obtain a stable PUF output without taking additional stabilization and error-correction techniques, e.g. temporal majority voting (TMV), pre-burning on PUF bits for end-of-life (EOL) prediction and reliability screening, masking algorithms, as well as leveraging parity bits for an Error-Correcting-Code (ECC) 3,4. This paper presents a PUF architecture fabricated in 55nm ultra-low-power (ULP) CMOS and 55nm embedded Flash. The scheme is able to produce reliable and uniformly random PUF output without the need for complex error correction or error bit testing.
Wu et al. (Thu,) studied this question.