A Data-Driven Defect Diagnosis and Failure Analysis Method for Mass-Production SRAM Redundancy Optimization

As the area occupied by static random access memory (SRAM) continues to increase in advanced integrated circuits, SRAM yield has become a critical factor that directly constrains chip cost and manufacturing efficiency. Conventional SRAM redundancy configuration methods are largely based on ideal random-defect assumptions and therefore cannot accurately characterize the systematic defects that are widely observed in advanced technology nodes. This mismatch often leads to suboptimal redundancy allocation with respect to the actual failure distribution. To address this issue, this paper proposes a data-driven SRAM redundancy optimization method for mass-production applications. The proposed method integrates defect distribution modeling, systematic defect identification, test-algorithm signature extraction, and physical failure analysis (PFA) into a closed-loop framework of test, diagnosis, localization, and optimization. Experimental results based on 7 nm mass-production chips demonstrate that the proposed method can effectively identify systematic defects, achieving an initial PFA localization hit rate close to 100% for single stuck-at faults while significantly improving failure analysis efficiency. Further redundancy evaluation shows that, after the major systematic defects are removed, the required redundancy can be reduced from two-row/two-column redundancy to only single-column redundancy while still covering all repairable failures, thereby improving both area efficiency and manufacturing economy. The proposed method provides a practical engineering solution for SRAM redundancy planning, process tuning, and yield improvement in advanced technology nodes.