Dense, 11 V-Tolerant, Balanced Stimulator IC with Digital Time-Domain Calibration for $< $100 nA Error

This is the authors' abstract. We don't add key points for this paper.

This article presents a multichannel neurostimulator implementing a novel charge balancing technique to achieve maximal integration. Safe neurostimulation demands accurate charge balancing of the stimulation waveforms to prevent charge build-up on the electrode-tissue interface. We propose digital time-domain calibration (DTDC), which adjusts the second phase of the biphasic stimulation pulses digitally, based on a one-time characterization of all stimulator channels with an on-chip ADC. Accurate control of the stimulation current amplitude is loosened in exchange for time-domain corrections, relieving circuit matching constraints and consequentially saving channel area. A theoretical analysis of DTDC is presented, establishing expressions for the required time resolution and the new, relaxed circuit matching constraints. To validate the DTDC principle, a 16-channel stimulator was implemented in 65 nm CMOS, requiring only 0.0141 mm <tex-math notation="LaTeX">²</tex-math> area/channel. Despite being implemented in a standard CMOS technology, 10.4 V compliance is achieved for compatibility with high-impedance microelectrode arrays typical for high-resolution neural prostheses. To the authors' knowledge, this is the first stimulator in a 65 nm low-voltage process achieving over 10 V output swing. Measurements after calibration show the DC error is successfully reduced below 96 nA on all channels. Static power consumption is 20.3 µW/channel.