Selective-Area Growth of InAs Nanowires on Ge and Vertical Transistor Application

III-V compound semiconductor and Ge are promising channel materials for future low-power and high-performance integrated circuits. A heterogeneous integration of these materials on the same platform, however, raises serious problem owing to a huge mismatch of carrier mobility. We proposed direct integration of perfectly vertically aligned InAs nanowires on Ge as a method for new alternative integrated circuits and demonstrated a high-performance InAs nanowire-vertical surrounding-gate transistor. Virtually 100% yield of vertically aligned InAs nanowires was achieved by controlling the initial surface of Ge and high-quality InAs nanowires were obtained regardless of lattice mismatch (6.7%). The transistor performance showed significantly higher conductivity with good gate control compared to Si-based conventional field-effect transistors: the drain current was 0.65 mA/μm, and the transconductance was 2.2 mS/μm at drain-source voltage of 0.50 V. These demonstrations are a first step for building alternative integrated circuits using vertical III-V/multigate planar Ge FETs.