Experimental evaluation demonstrates enhanced CMOS latchup immunity across varied smart power structures, indicating that substrate isolation and buried layers effectively eliminate parasitic faults.
This paper examines CMOS latchup immunity for a wide range of structures in a 0.25 mum smart power technology. The impact of logic ground isolation from the substrate and the presence of P+ and N+ buried layers below the logic wells is quantified
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Zhu et al. (2006) studied this question.
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