Optimization of Gate Current Profiles for SiC Power MOSFETs with Respect to Switching Loss, Overshoot, and Slew Rate

This paper addresses the challenge of optimally controlling silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) to minimize switching losses while simultaneously reducing overshoots and voltage slew rates. A digitally controlled gate current source is used to drive the transistors, and its output waveform is defined by a set of parameters that must be optimized. To this end, a sequential lowest segment extraction (SLSE) method is proposed to identify parameter sets that generate trade-off curves that closely approximate the Pareto frontiers. These curves represent the lowest simultaneously achievable values of either switching loss and current/voltage overshoot, or switching loss and maximum voltage slew rate. The resulting boundary curves demonstrate a total switching loss reduction of up to 60% while maintaining nearly the same overshoot and slew rate values compared to a classical gate driver. The paper concludes with an analysis of the results and a summary of the key findings.