Key result
An ASIC for real-time atrial fibrillation detection achieved a 44% area footprint reduction and up to 41X energy savings when operating at 1 kHz with a 300 mV supply voltage compared to 1.2 V.
Effect estimate: 41 X energy savings
The developed ASIC architecture for real-time atrial fibrillation detection achieves significant energy savings and area reduction, making it suitable for implantable loop recorders.
May enable longer ILR battery life; leaves open clinical validation of detection accuracy.
A real-time detector for episodes of atrial fibrillation is fabricated as an application specific integrated circuit (ASIC). The basis for detection is a set of three parameters for characterizing the RR interval series, i.e., turning point ratio, root mean square of successive differences, and Shannon entropy. The developed hardware architecture targets ultra-low voltage operation, suitable for implantable loop recorders with ultra-low energy requirements. Algorithmic and architectural optimizations are performed to minimize area and energy dissipation, with a total area footprint reduction of 44%. The design is fabricated in 65-nm CMOS low-leakage high-threshold technology. Measurements with aggressively scaled supply voltage (VDD) in the subthreshold (sub-VT) region show energy savings of up to 41 X when operating at 1 kHz with a VDD of 300 mV compared to a nominal VDD of 1.2 V.
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Andersson et al. (2014) studied Atrial fibrillation. ASIC for real-time atrial fibrillation detection vs. Nominal VDD of 1.2 V was evaluated on Energy savings and area footprint reduction (41 X energy savings). An ASIC for real-time atrial fibrillation detection achieved a 44% area footprint reduction and up to 41X energy savings when operating at 1 kHz with a 300 mV supply voltage compared to 1.2 V.
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