Delay analysis of Si NMOS Gbit/s logic circuits

A simple piecewise-linear analysis method which can be used to predict the logic propagation delay (/spl tau//SUB d/) for fine-line Si NMOS logic gates is presented. The set of equations derived shows explicitly the dependence of /spl tau//SUB d/ on inverter noise margins, driver transconductance, load current, node capacitance, driver and load input conductances, and driving waveshapes. Submicron-channel Si NMOS has demonstrated a /spl tau//SUB d/ as low as 30 ps for unity fan-in and fan-out ring oscillators. It is shown that the p-n junction capacitances of the driver and load devices account for up to 50% of the total logic gate capacitances. If reduced (as in SOI for example), Si NMOS logic gates might produce a /spl tau//SUB d/ as low as 15-20 ps. The delay analysis can be used to predict the operation of larger circuits. An example using a flip-flop frequency divider is given.