Key result
The FPGA-based ECG signal compression system achieved a maximum 90% compression rate with less than 9% signal distortion, a 5% improvement over state-of-the-art hardware implementations.
Why the study?
ECG signals often require compression for long-term recording and remote transmission in eHealth systems, needing precise real-time computation suitable for reconfigurable architectures.
Absolute Event Rate: 90% vs 85%
An FPGA-based ECG compression algorithm using FFT achieves up to 90% compression with minimal distortion and inherent high-frequency noise reduction, offering an efficient hardware solution for eHealth systems.
Electrocardiogram (ECG) is a record of the heart's electrical activity over a specified period, and it is the most popular noninvasive diagnostic test to identify several cardiac diseases. It is an integral part of a typical eHealth system, where the ECG signals are often needed to be compressed for long term data recording and remote transmission. Reconfigurable architecture offers high-speed parallel computation unit, particularly the Field Programmable Gate Array (FPGA) along with adaptable software features. Hence, this type of design is suitable for multi-channel signal processing units like ECGs, which usually require precise real-time computation. This paper presents a reconfigurable signal processing unit which is implemented in ZedBoard- a development board for Xilinx Zynq -7000 SoC. The compression algorithm is based on Fast Fourier Transformation. The implemented system can work in real-time and achieve a maximum 90% compression rate without any significant signal distortion (i.e., less than 9% normalized percentage of root-mean-square deviation). This compression rate is 5% higher than the state-of-the-art hardware implementation. Additionally, this algorithm has an inherent capability of high-frequency noise reduction, which makes it unique in this field. The confirmatory analysis is done using six databases from the PhysioNet databank to compare and validate the effectiveness of the proposed system.
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Chowdhury et al. (2019) studied ECG signal compression. FPGA-based reconfigurable architecture for ECG signal compression vs. State-of-the-art hardware implementations was evaluated on Maximum compression rate with less than 9% normalized percentage of root-mean-square deviation (PRDN). The FPGA-based ECG signal compression system achieved a maximum 90% compression rate with less than 9% signal distortion, a 5% improvement over state-of-the-art hardware implementations.
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